The present invention relates generally to integrated circuits and, more particularly, to a timing path slack monitoring system for an integrated circuit.
Research into VLSI (very large scale integration) degradation mechanisms suggests that timing performance deterioration could be a major concern in future process technologies. Therefore, a good deal of attention has to be paid to timing margins. A number of techniques have been proposed for detecting timing faults, errors induced by paths failing to meet timing requirements, in circuits while they are operating on line. There are also various classes of known monitors that are targeted at measuring circuit path delay. Canary or replica circuits are stand-alone circuits intended to mimic the timing behavior of the original circuits. The delay of the real circuit can be estimated through measuring delay of the replicas. Replica monitors are usually non-intrusive, but may fail to capture the variations that are local to real circuits such as random manufacturing variations and circuit aging. A measurement of timing slack at the end of critical paths however can capture the variations that are local to real circuits. Reductions in the amount of slack indicate that the circuit is degrading or aging and changes due to temperature, voltage and other fluctuations can be tracked, making timing slack a good measure of health. Since critical paths typically end at registers, some special flip-flops can be used as slack monitors.
“In-field aging measurement and calibration for power-performance optimization” by Wang et. al., DAC 2011, Jun. 5-10, 2011 describes an on-chip aging sensor that includes a master-slave flip-flop having a tap on the Q output of the master. A timing margin T (or slack) is assumed where T is defined as the difference between the time of arrival of a transition at the master and an input clock's rising edge. A pulse width W at the output of a series of logic gates coupled to the master and slave outputs bears a relation to T. A delay line, ring oscillator and counter are employed to measure W and thereby determine a value for T. A reduction in the measured value of T over time can signify aging of the integrated circuit whose paths are being monitored. One drawback of this circuit is that it can only discriminate against glitches on the input to the master, which are wider than a certain minimum duration. Accordingly, it would be advantageous to have a timing slack monitor circuit that also can discriminate from glitches on its output.